There is now an increasing interest in the semiconductor industry in high speed devices. A compound semiconductor material such as, for example, gallium-arsenide has an electron mobility about five times greater than that of monocrystalline silicon which is now widely applied to various integrated circuits. For this reason, research and development efforts have been continued to fabricate an integrated circuit on a substrate of compound semiconductor material. One of the fruits of the research and development efforts is disclosed in IEEE Ga-As IC Symposium Digests, 1984, pp. 121 to 124, in which memory circuits are realized on a gallium-arsenide substrate measuring 7.2 millimeters.times.6.2 millimeters. Prior arts related are also disclosed in IEEE ELECTRON DEVICE LETTERS, VOL. EDL-5, NO. 11, pp. 454 to 455, November 1984, and in ELECTRONIC COMMUNICATION SOCIETY PAPERS, VOL. 66, NO. 8, pp. 831 to 834, August 1983, respectively.
In the semiconductor industry, there is a soaring requirement to increase the number of transistors fabricated on a single semiconductor chip. One of the solutions is to use a chip having a large chip size. The memory device disclosed in the above paper has 16 K-bit memory cells on the gallium-arsenide substrate measuring 7.2 millimeters.times.6.2 millimeters. The maximum chip size is generally limited to 10 millimeters.times.10 millimeters in consideration of production yield so that it is necessary to have another solution to fabricate more than 64K-bit memory cells on a single gallium-arsenide semiconductor substrate.
Compound semiconductor substrates provide ease of fabrication for three dimensional integrated circuit because compound semiconductor layers are sequentially grown by suitable epitaxial techniques and then it is relatively easy to form miltilayer structures with channel layers insulated from each other. For this reason, a three-dimensional integrated circuit fabricated in a multilayer structure is another solution to increase the number of transistors without increasing a chip size.
A known example of a three-dimensional integrated circuit fabricated on a compound semiconductor material is illustrated in FIG. 1. A semi-insulating substrate 1 is prepared from a bulk wafer of gallium-arsenide. On the surface of the semi-insulating substrate 1 is epitaxially grown an n-type gallium-arsenide compound semiconductor layer 2 which in turn is covered with an undoped gallium-arsenide semiconductor layer 3. An n-type gallium-arsenide semiconductor layer 4 is epitaxially grown on the surface of the resultant structure. The undoped gallium-arsenide semiconductor layer is also grown by an usual epitaxial process and is partially removed by suitable etching techniques to expose selected portions of the surface of the n-type gallium-arsenide semiconductor layer 2 one of which is shown in FIG. 1. On the exposed portions of the gallium-arsenide semiconductor layer 2 as well as the selected portions of the gallium-arsenide semiconductor layer 4 is deposited a metal layer which is capable of providing a Schottky barrier therebetween. The metal layer is patterned and etched to form a plurality of gates 5 and 6 for field effect transistors forming parts of the integrated circuit. The gates 5 and 6 formed on the respective gallium-arsenide semiconductor layers 4 and 2 control depletion layers 7 and 8 extending into the surface portions of the gallium-arsenide semiconductor layers 4 and 2, respectively, and cause the currents flowing thereunder to vary in accordance with the control voltage applied to the gates 5 and 6.
The known three-dimensional integrated circuit has a drawback in that the field effect transistor formed with the gate 6 can not be disposed underneath the field effect transistor having the gate 5. This limits the number of the field effect transistors fabricated on the substrate 1. Further, the field effect transistors are alternately arranged on the gallium-arsenide semiconductor layers 2 and 4, then a wiring metal interconnecting the field effect transistors, such as two transistors shown in FIG. 1, tends to be elongated and, for this reason, signals on the wiring metal are delayed due to large parastic capacitance applied to the wiring metal.
This invention contemplates elimination of these drawbacks inherent in the conventional three-dimensional integrated circuit fabricated on a compound semiconductor substrate.